1. Field of the Invention
The present invention is directed to testing and screening of integrated circuit die to detect defective devices. More specifically, but without limitation thereto, the present invention is directed to a method of screening defective die by reducing variance in measured quiescent current due to process variations.
2. Description of Related Art
Quiescent current testing has proven to be an effective approach to screening defects during manufacturing and testing of semiconductor devices. As semiconductor technology progresses toward reduced transistor size, single limit quiescent current (IDDQ) testing becomes less effective due to large variances in quiescent current resulting from process shifts during manufacturing. The large variances in quiescent current are likely to result in screening good die as defective or in passing defective die.